module top(
           input m_rst_n,
           input m_clk,
           input m_ready,
           output m_valid,
           output [7: 0] m_data,

           input s_rst_n,
           input s_clk,
           input s_valid,
           output s_ready,
           input [7: 0] s_data,
           output [7: 0] data
       );

reg [7: 0] m_data_r;
reg m_valid_r;
reg m_ready_r;
reg m_ready_rr;
reg m_ready_rrr;
wire m_ready_rise;

//master,产生数据，产生valid信号
//检测m_ready的上升沿，进行数据切换
assign m_data = m_data_r;
assign m_valid = m_valid_r;
assign m_ready_rise = (~m_ready_rrr) & m_ready_rr;

always@(posedge m_clk or negedge m_rst_n)
	begin
		if (!m_rst_n)
			begin
				m_data_r <= 8'h00;
				m_valid_r <= 1'b0;
				m_ready_r <= 1'b0;
				m_ready_rr <= 1'b0;
				m_ready_rrr <= 1'b0;
			end
		else
			begin
				{m_ready_rrr, m_ready_rr, m_ready_r} <= {m_ready_rr, m_ready_r, m_ready};
				m_data_r <= (m_ready_rise == 1'b1) ? m_data_r + 1 : m_data_r;
				m_valid_r <= (m_ready_rr == 1'b1) ? 1'b1 : 1'b0;
			end
	end


reg s_ready_r;
reg s_valid_r;
reg s_valid_rr;
reg [7: 0] data_r;

//slave ,接受数据，产生ready信号
assign s_ready = s_ready_r;
assign data = data_r;

always@(posedge s_clk or negedge s_rst_n)
	begin
		if (!s_rst_n)
			begin
				s_ready_r <= 1'b0;
				s_valid_r <= 1'b0;
				s_valid_rr <= 1'b0;
				data_r <= 8'h00;
			end
		else
			begin
				{s_valid_rr, s_valid_r} <= {s_valid_r, s_valid};
				s_ready_r <= (s_valid_rr == 1'b0) ? 1'b1 : 1'b0;
				data_r <= (s_valid_rr == 1'b1) ? s_data : data_r;
			end
	end
endmodule
